Opsio - Cloud and AI Solutions
Populated green circuit board on edge-belt conveyor rails inside an automated optical inspection machine, under a black machine-vision camera with a white ring light on a linear gantry

AI Visual Inspection for Electronics & Semiconductors

Catch solder bridges and tombstoning, wafer scratches and display mura with a deep-learning layer on your AOI inspection that cuts false calls.

What is AI visual inspection for electronics and semiconductors?

AI visual inspection for electronics and semiconductors is deep-learning defect classification applied to AOI inspection, wafer and display images. Opsio adds it on top of your existing AOI, SPI and wafer inspection tools to classify three defect families: solder and placement defects on PCB assemblies, surface and pattern defects on wafers and dies, and luminance defects on display panels.

Key facts

  • Covers PCB solder joints, component placement, wafer surfaces, diced dies and display panels under test patterns.
  • Classifies images from existing 2D and 3D AOI, SPI and patterned-wafer inspection tools.
  • Edge inference runs in under 50 ms on NVIDIA Jetson or Intel OpenVINO hardware.
  • Maps decisions to IPC-A-610 Class 1, 2 or 3 acceptance criteria per product.
  • Links every result to a board serial, panel ID or wafer and die coordinate.
  • Connects to fab hosts through SECS/GEM and to SMT lines through IPC-CFX, OPC UA or PROFINET.
  • Stores images and results on the edge device, on-premises or in an EU cloud region.

Main defect families

Solder and placement defects
Faults in solder joints or component position on a PCB assembly, such as bridges, tombstones and wrong polarity.
Wafer and die defects
Scratches, particles, pattern faults, residue, edge chipping and cracks on silicon wafers or diced dies.
Display panel defects
Pixel faults, mura (uneven luminance or colour), light leakage and cosmetic damage on flat panels.

Last reviewed by Praveena Shenoy, Head of AI & Data, Opsio, a Swedish cloud and AI services company. Part of Opsio's AI Visual Inspection service.

Why is PCB, wafer and display inspection so hard to get right?

The hard part is not finding defects but separating real ones from false calls fast enough. An SMT line places tens of thousands of components per hour, and a rule-based AOI program flags anything that deviates from its thresholds. Shiny fillets, silkscreen near pads, a component from a second supplier or a slightly darker solder mask all trigger calls that are not defects.

Every false call costs operator time at the verification station. An operator who reviews hundreds of calls per shift starts to wave them through, and that is when a real solder bridge or a reversed diode escapes. Each new package or board revision means retuning the AOI library, often by one specialist per site.

Wafers and displays add their own physics. A particle or hairline scratch on a patterned wafer sits among repeating structures that scatter light, and a die crack after dicing can be a few micrometres wide. Mura (uneven luminance or colour) on a display panel is a low-contrast gradient that the eye adapts to within seconds, so manual grading varies by inspector and by hour.

Escapes are expensive at every level. A solder defect that passes in-circuit test can fail in the field and trigger a warranty return. A killer defect that reaches packaging wastes the cost of every later process step.

Where AI adds to AOI inspection, wafer review and panel test

Each use case below describes a real line, the mandatory defects for that stage, the imaging that suits them and the decision the station makes. Pick the stage that matches your bottleneck.

PCB assembly (SMT / AOI)

Macro of a circuit board after reflow: a chip component standing on one end (tombstoned) and a solder bridge joining two leads of a fine-pitch IC
Tombstoned chip component and solder bridge on a reflowed PCB

Situation

Your SMT line runs solder paste printing, SPI (solder paste inspection), pick-and-place, reflow and post-reflow AOI. The AOI calls every joint that breaks a rule, and operators re-verify each call at a review station before boards go to rework or onward.

Opsio does not replace your AOI. It reads the same images, classifies each call as a real defect or a false call, and handles new packages without rule rewriting. See how automated optical inspection works.

Defects

  • Missing componentAn empty pad pair, caused by a nozzle pick failure, an empty feeder or a part knocked off before reflow.
  • Misaligned or rotated componentA part shifted or skewed off its pads, caused by placement offset, board warp or paste slump during reflow.
  • Solder bridgeSolder joining two adjacent leads or pads, caused by excess paste, stencil misregistration or fine-pitch pads.
  • Tombstoninga chip component standing on one end after reflowCaused by unequal wetting forces when one pad melts first or carries more paste.
  • Insufficient solderA fillet too small to meet the acceptance class, caused by clogged apertures or poor paste release.
  • Excess solderA fillet that buries the termination or contacts the component body, caused by oversized apertures or double printing.
  • Lifted leadA gull-wing lead not in contact with its pad, caused by coplanarity faults or component warpage.
  • Wrong polarityA diode, capacitor or IC placed rotated 180°, caused by feeder loading errors or wrong program orientation.
  • Wrong component value or markingA correct footprint carrying the wrong part, caused by a mis-loaded reel or a changed supplier.

Inspection setup

Where your AOI already captures images, Opsio classifies them directly. For a new station, it uses a top-down colour area camera at typically 10 to 15 µm per pixel, telecentric lens and programmable multi-colour dome lighting that encodes fillet slope as colour. Four angled cameras see lifted leads and J-leads.

3D AOI (phase-shift structured light) adds solder volume and coplanarity. Stations sit after SPI and after reflow. The decision is pass, flag to the review station with the defect class, or route to rework, logged against the board serial.

Outcome

You get fewer false calls for operators to re-verify, while real defects still reach the review station. Typical gains show up as shorter review queues and fewer AOI library edits per new product introduction, measured per defect class in the feasibility study.

Wafer and die inspection

Patterned silicon wafer on a black chuck showing a fine diagonal scratch across the die grid and a scatter of small bright particles, with rainbow diffraction from the pattern
Patterned silicon wafer with a hairline scratch and surface particles visible under oblique light.

Situation

Your fab or back-end site already runs patterned-wafer inspection that outputs thousands of defect coordinates per wafer. Engineers review a sample on a review tool and classify them by hand, while diced dies are checked again before die attach.

Opsio adds die-level classification of the defects those tools flag, so review time goes to the defects that matter for yield. The model works on review images and defect files your tools already export, so the inspection recipe stays as it is.

Defects

  • ScratchA linear surface groove, caused by handling robots, CMP (chemical-mechanical polishing) debris or cassette contact.
  • ParticleForeign material on the surface, shed by tools, chemicals or the cleanroom environment.
  • Pattern defectbridging, opens or missing patternsA lithography or etch fault that shorts, breaks or omits a feature, caused by focus, dose or contamination issues.
  • Edge chippingMaterial broken from the wafer or die edge, caused by dicing blade wear, feed rate or handling.
  • ResidueLeftover resist, slurry or cleaning chemistry, caused by incomplete strip or rinse.
  • Die crack after dicingA fracture in the die body, caused by dicing stress, tape expansion or pick-up needle force.

Inspection setup

Wafer imaging uses bright-field microscopy for pattern defects and dark-field for scratches and particles, which scatter light into the lens. Line-scan cameras with TDI (time delay integration) sensors cover full wafers at typically 1 to 5 µm per pixel. The same dark-field logic drives strip and glass surface inspection.

Cleanroom hardware is sealed and low-particle, mounted outside the wafer path. Diced dies on film frames are imaged after dicing. The decision is bin, ink or flag for review, written to the wafer map and the yield system. Background: surface defect detection.

Outcome

You get a consistent defect class for every flagged location, not just a sample. Engineers review fewer nuisance defects, killer defects are prioritised in the wafer map, and die cracks are caught before die attach rather than at final test.

Classification results feed back into excursion control, so a rise in one defect class on one tool shows up within a lot rather than after a full yield report.

Display panels

Unbranded flat display panel in a dark inspection booth showing a uniform grey test field with faint cloudy brightness variation and a single dark pixel near the middle, camera mounted above
Display panel on a grey test pattern showing cloudy mura and a single dead pixel.

Situation

Your panel or module line drives each display through a set of test patterns before lamination or final assembly. Operators in a dark room grade pixel faults and uniformity by eye, often against limit samples.

Grading drifts between shifts because mura is a low-contrast gradient the eye adapts to. Panel sizes, resolutions and backplane types change with each product, and every new limit sample has to be explained to every inspector again.

Defects

  • Dead or stuck pixelA sub-pixel always off or always on, caused by TFT (thin-film transistor) faults, shorts or particles in the cell.
  • Murauneven luminance or colourA cloudy, line or spot variation in brightness, caused by cell-gap, backlight or OLED deposition non-uniformity.
  • ScratchSurface damage on the cover glass or polariser, caused by handling or transport.
  • Polariser bubbleTrapped air or a particle under the polariser film, caused by lamination pressure or contamination.
  • Edge chipGlass broken at the panel edge, caused by scribing, breaking or handling.
  • Light leakageBright areas on a black pattern, caused by backlight gaps, frame pressure or polariser misalignment.

Inspection setup

A pattern generator cycles white, black, grey levels and RGB fields. A high-resolution monochrome camera, typically with three or more sensor pixels per display pixel, images each pattern in a darkened enclosure; a colour or colorimetric camera adds colour mura.

Flat-field correction removes lens fall-off before the model looks for low-contrast mura. A low-angle light covers scratches and edge chips. Read more on machine vision cameras. The decision is grade, route to repair or reject, logged against the panel ID.

Outcome

You get repeatable mura and pixel grading that does not depend on who is in the dark room. Each panel carries its images and grade, so you can trace a field return to the original test result and adjust the limit with evidence.

New panel sizes and resolutions are added by imaging a set of graded panels, not by rebuilding a rule set. The same flat-field and pattern logic carries across LCD and OLED products.

How AOI inspection with deep learning runs on your SMT line

The same six steps apply on an SMT line, a back-end wafer tool or a panel tester; this walk-through uses the SMT case.

Machine-vision camera with a downward-facing lens and LED ring light on an aluminium profile gantry over a conveyor carrying a populated circuit board
Inspection station with ring-lit industrial camera over a circuit board on an SMT conveyor.
  1. 1

    Trigger and part presentation

    The board arrives on the conveyor and an IPC-HERMES-9852 or SMEMA handshake stops it under the head. Fiducials fix board position before imaging.

  2. 2

    Image acquisition

    A GigE Vision or USB3 Vision camera with telecentric lens captures each field of view under the dome, plus 3D projector frames where fitted. An ESD-safe enclosure blocks ambient light.

  3. 3

    Edge inference and latency budget

    An NVIDIA Jetson or Intel OpenVINO device classifies each AOI call in under 50 ms, so the board leaves the station within the line beat.

  4. 4

    Decision and actuation

    The verdict goes to the line over IPC-CFX, OPC UA or PROFINET. A diverter gate sends flagged boards to the review or rework buffer.

  5. 5

    Traceability and data retention

    Images, defect class and confidence are stored against board serial and reference designator. Retention follows your quality policy on the edge, on-premises or in an EU cloud.

  6. 6

    Active-learning loop

    Operator verdicts at the review station feed back as labels. New packages, board revisions and defect classes are retrained in SageMaker without rewriting AOI rules.

Imaging methods for solder joint inspection, wafers and displays

Each defect family has a standard imaging method; the model is only as good as the image it receives.

Defect familyBest-suited imagingWhy
Solder fillets: solder bridge, insufficient and excess solderMulti-colour dome lighting (2D) plus 3D AOI phase-shift structured light for solder joint inspectionColour bands encode fillet slope; the 3D height map measures solder volume.
Missing, misaligned, rotated components and tombstoningTop-down bright-field colour camera plus angled side camerasBody outline and pad overlap show position; side views show a part standing on end.
Lifted leads and coplanarity3D AOI (phase-shift structured light) and angled camerasLead height above the pad is invisible in a straight top-down 2D image.
Wrong polarity, value or markingHigh-resolution colour bright-field with OCR on part markingsPolarity marks and printed codes need sharp, even, glare-free light.
Wafer scratches, particles and residueDark-field microscopy and high-resolution line-scanRaised or grooved features scatter light into the lens against a dark background.
Pattern defects: bridging, opens, missing patternsBright-field microscopy with die-to-die comparisonReflected light shows feature shape; neighbouring dies act as the reference, like golden-template print inspection.
Die crack and edge chippingBright-field and dark-field die imaging after dicingCracks and chips scatter light along fracture edges at micrometre scale.
Dead pixels and mura (mura detection)High-resolution monochrome or colorimetric camera on test patterns, flat-field corrected, dark boothDriven patterns expose pixel faults; correction makes faint luminance gradients measurable.
Light leakage, polariser bubbles, scratches, edge chipsBlack-pattern imaging plus low-angle and backlightLeakage shows on black; bubbles and scratches catch grazing light.

Integration with MES, SPC and IPC-A-610 acceptance classes

The system reads what your line already produces and writes results where your quality team already looks.

What it reads
AOI and SPI images and call lists, board serials and reference designators from your MES, wafer maps and defect files from inspection tools, and panel IDs from the pattern generator.
What it writes
Per-call verdicts and defect classes to the review station and MES, SPC data on defect rates per position, and bin or ink codes to the wafer map and yield system.
IPC-A-610 acceptance classes
Supports IPC-A-610 Class 1, 2 and 3 as configurable thresholds per product, so a Class 3 board is judged on stricter fillet and placement criteria than a Class 1 board.
SPC feedback to print, placement and reflow
Defect trends per position feed back to the printer, pick-and-place and reflow profile, so a drifting stencil shows up before it produces bridges.
SECS/GEM in semiconductor fabs
Designed to meet the requirements of SECS/GEM (SEMI E5/E30) host communication, reporting results and alarms to the fab host and MES.
Where data lives
Images stay on the edge device or on-premises; training data can sit in an EU cloud region. You own the data and decide retention.

From first test to your line in five steps

Every project starts with your own boards, wafers or panels in the Opsio AI Lab, not with a slide deck.

  1. 1

    Opsio runs tests in the AI Lab

    You ship typically 20 to 50 good boards and 10 to 30 examples of each defect class you care about: bridges, tombstones, polarity, insufficient solder, lifted leads. Saved AOI images with operator verdicts count. For wafers and displays, defect review images and a few graded panels work. Opsio trains a first model and measures detection and false-reject rate per class.

    You provide
    Sample boards, wafers, dies or panels; AOI images with verdicts; your IPC-A-610 class and limit samples.
    Opsio delivers
    Lab imaging with candidate cameras and lighting, a first trained model and per-class results.
  2. 2

    Present results and pricing

    You see per-defect detection and false-call results, example images of hits and misses, and how the model handles boards it has not seen. Opsio recommends whether to reuse your AOI images or add a camera, confirms cycle-time fit against your line beat, and gives a fixed quote for the production system and managed service.

    You provide
    Line beat, AOI model and export options, MES and review station details.
    Opsio delivers
    Results review, camera and lighting bill of materials, cycle-time check and fixed quote.
  3. 3

    Decision and PO/MSA signing

    You decide. The purchase order and master services agreement fix the scope, acceptance criteria per defect class, data ownership, retention and support levels. Acceptance criteria are written in your terms, for example maximum false calls per board at your IPC-A-610 class.

    You provide
    Decision, purchase order and agreed acceptance criteria.
    Opsio delivers
    Master services agreement, project plan and named contacts.
  4. 4

    Installation in the Opsio AI Lab

    Opsio builds and commissions the production station in the AI Lab on the real camera, lighting, enclosure and edge hardware. The station is tested against your acceptance criteria with your boards or panels, and the interfaces to your AOI, MES or SECS/GEM host are simulated and checked.

    You provide
    Further sample parts if needed and interface specifications.
    Opsio delivers
    Pre-commissioned station, test report against acceptance criteria and interface checks.
  5. 5

    Installation at the customer location

    The station is installed on your line and connected to the AOI, MES and review station. It runs in shadow mode next to your current inspection, so you compare verdicts board by board, then switches to live decisions. Operators are trained and the active-learning loop starts.

    You provide
    Line access, a shadow-mode window and operator time for training.
    Opsio delivers
    Installation, integration, shadow-mode report, go-live, training and managed service.

Pricing for the feasibility study, production stations and the managed service is on the AI Visual Inspection service page.

AI visual inspection for Electronics & Semiconductors: questions

What is a PCB inspection?

A PCB inspection checks a bare or assembled circuit board for defects before it moves on. On an assembly line it includes SPI after printing, AOI after placement and reflow, AXI for hidden joints and electrical tests such as in-circuit and functional test. Visual inspection catches placement and solder faults early, before they are buried under further assembly.

What is a solder bridge?

A solder bridge is unwanted solder joining two leads or pads that should be electrically separate. It usually comes from excess paste, stencil misregistration or fine-pitch pads. On the line, 2D AOI sees the bridge as a continuous bright band between leads, and the deep-learning layer separates true bridges from reflections and silkscreen that rule-based AOI often calls by mistake.

What is tombstoning in PCB assembly?

Tombstoning is a chip component standing on one end after reflow, soldered to only one pad. It happens when one pad wets before the other or carries more paste, so surface tension lifts the part. Angled cameras and 3D AOI show the raised body clearly, and the model learns tombstones across package sizes from 0201 upwards without separate rules per size.

How do you check for bad solder joints?

You check solder joints by imaging each fillet under multi-angle lighting and comparing its shape and volume with the acceptance criteria. Colour dome lighting shows fillet slope, 3D AOI measures volume and height, and X-ray covers hidden joints such as BGAs. AI classification sorts each call into bridge, insufficient, excess, lifted lead or false call, so operators only re-check real candidates.

How does dead pixel detection work on a panel line?

Dead pixel detection works by driving the panel to uniform test patterns and imaging it with a camera that has several sensor pixels per display pixel. A dead sub-pixel shows as a dark point on white or colour fields; a stuck one shows as a bright point on black. The system records the pixel coordinate, colour channel and pattern for each fault.

How does mura detection work?

Mura detection works by imaging the panel on grey and colour test patterns, removing lens and sensor non-uniformity with flat-field correction, then finding low-contrast luminance or colour gradients. Deep learning helps because mura shapes vary: clouds, bands, spots and edge glow. The model grades each region against your limit samples instead of a single global threshold.

What is wafer defect inspection?

Wafer defect inspection finds and classifies scratches, particles, pattern defects and residue on wafers between process steps. Patterned-wafer tools use bright-field and dark-field optics to flag defect coordinates; review and classification then decide which are killer defects. Opsio works at the classification stage, labelling each flagged defect so engineers review the ones that affect yield.

What is 3D AOI inspection?

3D AOI inspection measures height on the board as well as the 2D image, usually with phase-shift structured light projected from several angles. It adds solder volume, component coplanarity and lifted-lead height. The deep-learning layer uses the height map together with the colour image, which helps on reflective fillets and dark components where 2D images are ambiguous.

What is the difference between AOI and AXI inspection?

AOI uses visible light and sees only what is on the surface; AXI (automated X-ray inspection) sees through components to hidden joints. AOI covers placement, polarity, visible fillets and bridges at line speed. AXI is used for BGAs, QFNs and bottom-terminated parts where joints are hidden. AI classification works on both image types, but this page focuses on optical inspection.

Can AOI inspect through-hole components?

Yes, AOI can inspect through-hole components, usually from the solder side after wave or selective soldering. It checks pin protrusion, fillet shape, bridges between pins and missing solder. Through-hole joints vary more than SMT joints, which produces many rule-based false calls, so a trained model that has seen your real good and bad joints usually helps most here.

What does AOI programming involve?

AOI programming means building a library of inspection rules for every package, footprint and board, then tuning thresholds until false calls are acceptable. Each new package or revision needs more tuning. A deep-learning layer reduces that work: it learns from labelled AOI images and operator verdicts, so new packages are added by labelling examples rather than rewriting rules.

What does an AOI false call mean?

An AOI false call is a joint or component the AOI flags as defective that an operator then judges acceptable. False calls come from tight thresholds, reflections, silkscreen, supplier changes and board colour variation. They cost operator re-verification time and train operators to approve calls quickly, which raises the risk of escapes. Reducing false calls is the main economic case on SMT lines.

What is the difference between wafer inspection and metrology?

Wafer inspection looks for defects anywhere on the wafer; metrology measures specific dimensions such as film thickness, critical dimension and overlay at chosen sites. Inspection answers what is wrong and where; metrology answers whether a feature is within specification. AI classification adds most value on inspection output, where thousands of flagged defects need sorting.

What is the IPC-A-610 standard?

IPC-A-610 is the industry acceptance standard for electronic assemblies, defining what target, acceptable and defect conditions look like for solder joints and components. It sets three product classes: Class 1 general, Class 2 dedicated service and Class 3 high performance. An inspection system can apply class-specific thresholds; it does not certify your product or your operators.

How should a solder joint look?

A good solder joint shows a smooth, concave fillet that wets both the pad and the termination, with the lead outline visible. IPC-A-610 sets minimum fillet height, side overhang and end-joint width by component type and class. Dull, grainy, convex or non-wetted joints are indicators to check. These criteria become the labels the model learns.

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